// $Module: reg_ive_sad $
// $RegisterBank Version: V 1.0.00 $
// $Author: andy.tsao $
// $Date: Tue, 07 Dec 2021 11:00:55 AM $
//

//GEN REG ADDR/OFFSET/MASK
#define  IVE_SAD_REG_SAD_00  0x0
#define  IVE_SAD_REG_SAD_01  0x4
#define  IVE_SAD_REG_SAD_02  0x8
#define  IVE_SAD_REG_SAD_03  0xc
#define  IVE_SAD_REG_SAD_04  0x10
#define  IVE_SAD_REG_SAD_05  0x14
#define  IVE_SAD_REG_SAD_06  0x18
#define  IVE_SAD_REG_SAD_ENMODE   0x0
#define  IVE_SAD_REG_SAD_ENMODE_OFFSET 0
#define  IVE_SAD_REG_SAD_ENMODE_MASK   0x3
#define  IVE_SAD_REG_SAD_ENMODE_BITS   0x2
#define  IVE_SAD_REG_SAD_OUT_CTRL   0x0
#define  IVE_SAD_REG_SAD_OUT_CTRL_OFFSET 4
#define  IVE_SAD_REG_SAD_OUT_CTRL_MASK   0x70
#define  IVE_SAD_REG_SAD_OUT_CTRL_BITS   0x3
#define  IVE_SAD_REG_SAD_U16BIT_THR   0x0
#define  IVE_SAD_REG_SAD_U16BIT_THR_OFFSET 8
#define  IVE_SAD_REG_SAD_U16BIT_THR_MASK   0xffff00
#define  IVE_SAD_REG_SAD_U16BIT_THR_BITS   0x10
#define  IVE_SAD_REG_SAD_SHDW_SEL   0x0
#define  IVE_SAD_REG_SAD_SHDW_SEL_OFFSET 24
#define  IVE_SAD_REG_SAD_SHDW_SEL_MASK   0x1000000
#define  IVE_SAD_REG_SAD_SHDW_SEL_BITS   0x1
#define  IVE_SAD_REG_SAD_U8BIT_MAX   0x4
#define  IVE_SAD_REG_SAD_U8BIT_MAX_OFFSET 0
#define  IVE_SAD_REG_SAD_U8BIT_MAX_MASK   0xff
#define  IVE_SAD_REG_SAD_U8BIT_MAX_BITS   0x8
#define  IVE_SAD_REG_SAD_U8BIT_MIN   0x4
#define  IVE_SAD_REG_SAD_U8BIT_MIN_OFFSET 8
#define  IVE_SAD_REG_SAD_U8BIT_MIN_MASK   0xff00
#define  IVE_SAD_REG_SAD_U8BIT_MIN_BITS   0x8
#define  IVE_SAD_REG_SAD_ENABLE   0x8
#define  IVE_SAD_REG_SAD_ENABLE_OFFSET 0
#define  IVE_SAD_REG_SAD_ENABLE_MASK   0x1
#define  IVE_SAD_REG_SAD_ENABLE_BITS   0x1
#define  IVE_SAD_REG_FORCE_CLK_ENABLE   0xc
#define  IVE_SAD_REG_FORCE_CLK_ENABLE_OFFSET 0
#define  IVE_SAD_REG_FORCE_CLK_ENABLE_MASK   0x1
#define  IVE_SAD_REG_FORCE_CLK_ENABLE_BITS   0x1
#define  IVE_SAD_REG_PROB_GRID_V   0x10
#define  IVE_SAD_REG_PROB_GRID_V_OFFSET 0
#define  IVE_SAD_REG_PROB_GRID_V_MASK   0xfff
#define  IVE_SAD_REG_PROB_GRID_V_BITS   0xc
#define  IVE_SAD_REG_PROB_GRID_H   0x10
#define  IVE_SAD_REG_PROB_GRID_H_OFFSET 12
#define  IVE_SAD_REG_PROB_GRID_H_MASK   0xfff000
#define  IVE_SAD_REG_PROB_GRID_H_BITS   0xc
#define  IVE_SAD_REG_PROB_PIX_V   0x10
#define  IVE_SAD_REG_PROB_PIX_V_OFFSET 24
#define  IVE_SAD_REG_PROB_PIX_V_MASK   0xf000000
#define  IVE_SAD_REG_PROB_PIX_V_BITS   0x4
#define  IVE_SAD_REG_PROB_PIX_H   0x10
#define  IVE_SAD_REG_PROB_PIX_H_OFFSET 28
#define  IVE_SAD_REG_PROB_PIX_H_MASK   0xf0000000
#define  IVE_SAD_REG_PROB_PIX_H_BITS   0x4
#define  IVE_SAD_REG_PROB_PREV_SUM   0x14
#define  IVE_SAD_REG_PROB_PREV_SUM_OFFSET 0
#define  IVE_SAD_REG_PROB_PREV_SUM_MASK   0xffff
#define  IVE_SAD_REG_PROB_PREV_SUM_BITS   0x10
#define  IVE_SAD_REG_PROB_CURR_PIX_0   0x14
#define  IVE_SAD_REG_PROB_CURR_PIX_0_OFFSET 16
#define  IVE_SAD_REG_PROB_CURR_PIX_0_MASK   0xff0000
#define  IVE_SAD_REG_PROB_CURR_PIX_0_BITS   0x8
#define  IVE_SAD_REG_PROB_CURR_PIX_1   0x14
#define  IVE_SAD_REG_PROB_CURR_PIX_1_OFFSET 24
#define  IVE_SAD_REG_PROB_CURR_PIX_1_MASK   0xff000000
#define  IVE_SAD_REG_PROB_CURR_PIX_1_BITS   0x8
#define  IVE_SAD_REG_PROB_EN   0x18
#define  IVE_SAD_REG_PROB_EN_OFFSET 0
#define  IVE_SAD_REG_PROB_EN_MASK   0x1
#define  IVE_SAD_REG_PROB_EN_BITS   0x1
